1. Field of the Invention
The present invention generally relates to a layout pattern of a photomask, and more particularly to a calculation method for generating a layout pattern in a photomask.
2. Description of the Prior Art
As the integrated circuit (IC) manufacturing industry moves towards smaller device dimensions, the resolution enhancement techniques (RET) for optical lithography such as off-axis illumination (OAI), optical proximity correction (OPC) and the phase-shifting mask (PSM) have been implemented in conjunction with reducing the wavelength of optical exposure.
Currently, in order to further increase the depth-of-focus (DOF) during a photolithography process, layout patterns on the photomasks are often designed to have different thicknesses. In this way, the optical path between the layout patterns and a layer to be printed with the layout patterns may be adjusted. Accordingly, the DOF corresponding to certain regions of the layout pattern may be increased so as to increase the exposure resolution during the photolithographic process.
However, there are still some optical problems, such as flares and distortions, which cannot be solved effectively even if the photomasks are designed to have the layout patterns in different thicknesses. As a result, how to generate layout patterns on photomasks so as to overcome these optical problems is still a big issue nowadays.